1. Technical Field
The present invention relates in general to cache controllers in data processing systems and in particular to cache controllers which layer cache and architectural specific functions. Still more particularly, the present invention relates to symmetric treatment of operations within a layered cache controller design.
2. Description of the Related Art
Data processing systems which utilize a level two (L2) cache typically include a cache controller for managing transactions affecting the cache. Such cache controllers are conventionally implemented on a functional level, as depicted in FIG. 5. For example, a cache controller 502 may include logic 504 for maintaining the cache directory, logic 506 for implementing a least recently used (LRU) replacement policy, logic for managing reload buffers 508, and logic for managing store-back buffers 510. In traditional implementations, the cache is generally very visible to these and other architectural functions typically required for cache controllers, with the result that cache controller designs are specific to a particular processors such as the PowerPC.TM., Alpha.TM., or the x86 family of processors.
In multiprocessor systems, the cache controller must support operations which may either be initiated by an upstream or local processor or initiated by a horizontal or non-local processor and snooped on the system bus by the cache controller. Therefore, a conventional implementation includes both processor-side logic 514 and system-side logic 516 for handling specific operations. Since similar operations may be initiated by either a local processor or a horizontal processor, logic 514 and 516 may be substantially duplicative. The duplicative logic is included, however, for the purpose of accelerating response to an architectural operation initiated by a local processor.
The controller design depicted in FIG. 5 requires duplicative, complex, silicon-intensive logic for responding architectural operations initiated either by a local processor or by a horizontal processor or lower level cache. The design also requires interlocks between units within the controller which respond to different operations.
It would be desirable, therefore, to implement a cache controller which avoids duplication of logic required to respond to a given operation. It would further be advantageous to provide a cache controller design eliminating the need for interlock logic relating to architectural operations within the cache controller.